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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">CTILSR, CTI Lock Status Register</h1><p>The CTILSR characteristics are:</p><h2>Purpose</h2>
        <p>Indicates the current status of the Software Lock for CTI registers.</p>

      
        <p>The optional Software Lock provides a lock to prevent memory-mapped writes to the Cross-Trigger Interface registers. Use of this lock mechanism reduces the risk of accidental damage to the contents of the Cross-Trigger Interface registers. It does not, and cannot, prevent all accidental or malicious damage.</p>
      <h2>Configuration</h2><p>CTILSR is in the Debug power domain.
    </p>
        <p>If <span class="xref">FEAT_Debugv8p4</span> is implemented, the Software Lock is not implemented.</p>

      
        <p>Software uses <a href="ext-ctilar.html">CTILAR</a> to set or clear the lock, and CTILSR to check the current status of the lock.</p>
      <h2>Attributes</h2>
        <p>CTILSR is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="29"><a href="#fieldset_0-31_3">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-2_2">nTT</a></td><td class="lr" colspan="1"><a href="#fieldset_0-1_1-1">SLK</a></td><td class="lr" colspan="1"><a href="#fieldset_0-0_0">SLI</a></td></tr></tbody></table><h4 id="fieldset_0-31_3">Bits [31:3]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-2_2">nTT, bit [2]</h4><div class="field">
      <p>Not thirty-two bit access required. RAZ.</p>
    </div><h4 id="fieldset_0-1_1-1">SLK, bit [1]<span class="condition"><br/>When Software Lock is implemented:
                        </span></h4><div class="field"><p>Software Lock status for this component. For an access to LSR that is not a memory-mapped access, or when the Software Lock is not implemented, this field is <span class="arm-defined-word">RES0</span>.</p>
<p>For memory-mapped accesses when the Software Lock is implemented, possible values of this field are:</p><table class="valuetable"><tr><th>SLK</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Lock clear. Writes are permitted to this component's registers.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Lock set. Writes to this component's registers are ignored, and reads have no side effects.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On an External debug reset, 
      this field resets
       to <span class="binarynumber">1</span>.
</li></ul></div><h4 id="fieldset_0-1_1-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, RAZ.</p>
    </div><h4 id="fieldset_0-0_0">SLI, bit [0]</h4><div class="field">
      <p>Software Lock implemented. For an access to LSR that is not a memory-mapped access, this field is RAZ. For memory-mapped accesses, the value of this field is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span>. Permitted values are:</p>
    <table class="valuetable"><tr><th>SLI</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Software Lock not implemented or not memory-mapped access.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Software Lock implemented and memory-mapped access.</p>
        </td></tr></table></div><h2>Accessing CTILSR</h2><h4>CTILSR can be accessed through the memory-mapped interfaces:</h4><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th></tr><tr><td>CTI</td><td><span class="hexnumber">0xFB4</span></td><td>CTILSR</td></tr></table><p>Accesses on this interface are <span class="access_level">RO</span>.</p><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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